IC設計高級工程師 采微科技 上海采微電子科技有限公司,上海采微科技,采微科技 崗位職責
1.Participate in RISCV or Deep Learning Accelerator or other SOC 地址 design for all frontend phase
2.Specification define
3.RTL implementation
4.Analysis and optimization for performance
5.Analysis and optimization for power
6.Analysis and optimization for timing
7.Design flow: lint/synthesis/sta/formal check
8.Silicon debugging
任職條件
1.MS with 5+ or 3+ years of experience in ASIC design
2.Experience with RISC CPU (RISCV/M地址S/ARM) related 地址s design are highly desirable
3.Experience with USB/M地址I_CSI/M地址I_DSI or other high speed interface 地址s design are highly desirable
4.Experience with Deep Learning Accelerator related 地址s design are highly desirable
5.Experience with all phases of frontend architecture, design and validation
6.RTL Coding, design reviews, SYN, CDC, FEV
7.Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8.Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9.Good experience in scripting languages like Perl, Unix shell or similar languages
1.Participate in RISCV or Deep Learning Accelerator or other SOC 地址 design for all frontend phase
2.Specification define
3.RTL implementation
4.Analysis and optimization for performance
5.Analysis and optimization for power
6.Analysis and optimization for timing
7.Design flow: lint/synthesis/sta/formal check
8.Silicon debugging
任職條件
1.MS with 5+ or 3+ years of experience in ASIC design
2.Experience with RISC CPU (RISCV/M地址S/ARM) related 地址s design are highly desirable
3.Experience with USB/M地址I_CSI/M地址I_DSI or other high speed interface 地址s design are highly desirable
4.Experience with Deep Learning Accelerator related 地址s design are highly desirable
5.Experience with all phases of frontend architecture, design and validation
6.RTL Coding, design reviews, SYN, CDC, FEV
7.Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8.Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9.Good experience in scripting languages like Perl, Unix shell or similar languages
收藏